This application relies for priority upon Korean Patent Application No. 2000-03708, filed on Jan. 26, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to electrical devices and, more particularly, to a system having memory devices operable in a common interface.
Recently various memory devices are being employed in computer- or microprocessor-based systems. Such systems require data storage elements, such memories. These memories include volatile semiconductor memory devices, e.g. dynamic random access memory devices (DRAMs) and static random access memory devices (SRAMs), and non-volatile semiconductor memory devices, e.g. NAND-type flash memory devices and NOR-type flash memory devices. The volatile and non-volatile semiconductor memory devices are controlled by their corresponding memory controllers. Such memory controllers are disclosed in U. S. Pat. Nos. 5,684,978, and 5,893,136.
As well known in the art, DRAM and SRAM devices adopt an interface mode where address pins are separated from data pins, while a NAND-type flash memory device adopts an interface mode (i.e., xe2x80x9cmultiplexing interface modexe2x80x9d) where address pins are commonly used with data pins. The above NAND-type flash memory device is disclosed in a data book xe2x80x9cFlash Memoriesxe2x80x9d published in Samsung Electronics Co., Ltd., March 1998. The above DRAM device is disclosed in a data book xe2x80x9cMOS Memoryxe2x80x9d published by Samsung Electronics Co., Ltd., 1995. And, the above SRAM device is disclosed in a data book xe2x80x9cSRAM/FIFOxe2x80x9d published in Samsung Electronics Co., Ltd., April 1995.
A conventional system is schematically shown in FIG. 1 The system includes a microprocessor 1 (or a central processing unit, a baseband modem of a communication terminal, a codec, etc.), a DRAM device 2, an SRAM device 3, and a NAND-type flash memory device 4. The microprocessor 1 includes memory controllers 5, 6, and 7 that control the DRAM device 2, the SRAM device 3, and the NAND-type flash memory device 4, respectively. The memory controller 5 for the only DRAM device transfers address and control signals to the DRAM device 2 through a corresponding bus 15. The memory controller 6 for the only SRAM device transfers address and control signals to the SRAM device 3 through a corresponding bus 16. And the memory controller 7 for the NAND-type flash memory device transfers address and control signals to the NAND-type flash memory device 4 through a corresponding bus 17.
Since memory devices used in a system have pin arrangements and interface modes that are different from each other, a memory controller must be provided for each of memory devices 2, 3, 4, to the microcontroller 1, as can be seen in FIG. 1. This causes increase in a size of the microcontroller 1. In addition, memory devices having pin arrangements and interface modes that are different from each other cannot be mounted together within a single chip-size package (CSP).
It is therefore an object of the present invention to provide a system having NAND interface DRAM, SRAM, and NOR-type flash memory devices which are commonly connected to one bus.
It is another object of the present invention to provide a NAND-type flash memory device having an SRAM interface mode.
It is further another object of the present invention to provide a NAND-type flash memory device capable of enhancing a bus use efficiency.
A semiconductor memory device includes a random access memory chip, and a package containing the random access memory chip. The package includes a plurality of pins for electrically connecting the random access memory chip to an external device.
According to one aspect of the present invention, the pins provide memory functions commonly to a random access memory device, and also to an electrically erasable and programmable non-volatile semiconductor memory device. Each of the pins is arranged at a position of a pin corresponding to the non-volatile semiconductor memory device.
According to another aspect of the present invention, the pins include a first group of pins and a second group of pins. The pins of the first group provide memory functions commonly to a static random access memory device and also to an electrically erasable and programmable non-volatile semiconductor memory device. And the pins of the first group are arranged at positions of corresponding pins of the static random access memory device, respectively. The pins of the second group provide functions of unused non-volatile semiconductor memory device to the static random access memory. The pins of the second group are arranged at a position of an unused pin of the static random access memory, respectively.